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IDT71321SA/LA HIGH SPEED IDT71421SA/LA 2K X 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
Features
x
x
x
High-speed access - Commercial: 20/25/35/55ns (max.) - Industrial: 55ns (max.) Low-power operation - IDT71321/IDT71421SA -- Active: 325mW (typ.) -- Standby: 5mW (typ.) - IDT71321/421LA -- Active: 325mW (typ.) -- Standby: 1mW (typ.) Two INT flags for port-to-port communications
x
x x x x x x x
MASTER IDT71321 easily expands data bus width to 16-ormore-bits using SLAVE IDT71421 On-chip port arbitration logic (IDT71321 only) BUSY output flag on IDT71321; BUSY input on IDT71421 Fully asynchronous operation from either port Battery backup operation - 2V data retention (LA only) TTL-compatible, single 5V 10% power supply Available in 52-Pin PLCC, 64-Pin TQFP, and 64-Pin STQFP Industrial temperature range (-40C to +85C) is available for selected speeds
Functional Block Diagram
OEL CEL R/WL OER CER R/WR
I/O0L- I/O7L I/O Control BUSYL A10L A0L
(1,2)
I/O Control
I/O0R-I/O7R
BUSYR Address Decoder
11
(1,2)
MEMORY ARRAY
11
Address Decoder
A10R A0R
CEL OEL R/WL
ARBITRATION and INTERRUPT LOGIC
CER OER R/WR
INTL
(2)
INTR
2691 drw 01
(2)
NOTES: 1. IDT71321 (MASTER): BUSY is open drain output and requires pullup resistor of 270. IDT71421 (SLAVE): BUSY is input. 2. Open drain output: requires pullup resistor of 270.
MARCH 1999
1
(c)1999 Integrated Device Technology, Inc. DSC-2691/8
1
IDT71321SA/LA and IDT71421SA/LA High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Description
The IDT71321/IDT71421 are high-speed 2K x 8 Dual-Port Static RAMs with internal interrupt logic for interprocessor communications. The IDT71321 is designed to be used as a stand-alone 8-bit DualPort Static RAM or as a "MASTER" Dual-Port Static RAM together with the IDT71421 "SLAVE" Dual-Port in 16-bit-or-more word width systems. Using the IDT MASTER/SLAVE Dual-Port Static RAM approach in 16-or-more-bit memory system applications results in full speed, error-free operation without the need for additional discrete logic. Both devices provide two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature, controlled by CE, permits the on chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 325mW of power. Low-power (LA) versions offer battery backup data retention capability, with each DualPort typically consuming 200W from a 2V battery. The IDT71321/IDT71421 devices are packaged in 52-pin PLCCs, 64-pin TQFPs, and 64-pin STQFPs.
R/W L CE L V CC CER R/W R BUSYR
Pin Configurations(1,2,3)
INT L BUSYL
INDEX A1L A 2L A 3L A 4L A 5L A 6L A 7L A 8L A 9L I/O 0L I/O 1L I/O 2L I/O 3L
87 6 5 4 3 2 1 52 51 50 49 48 47 46 45 9 10 44 11 43 12 42 IDT71321/421J 13 41 J52-1(4) 14 40 15 39 PLCC 38 16 Top View(5) 37 17 18 36 19 35 20 34 21 22 23 24 25 26 27 28 29 30 31 32 33
A0L OE L A10L
INTR A10R
OE R A 0R A 1R A 2R A 3R A 4R A 5R A 6R A 7R A 8R A 9R NC I/O7R
2691 drw 02
INDEX OEL A0L A1L A2L A3L A4L A5L A6L N/C A7L A8L A9L N/C I/O0L I/O1L I/O2L
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
N/C N/C A10L INTL BUSYL R/WL CEL VCC VCC CER R/WR BUSYR INTR A10R N/C N/C
,
I/O 4L I/O 5L I/O 6L I/O 7L
I/O 0R I/O 1R I/O 2R I/O 3R I/O 4R I/O 5R I/O 6R
NC GND
2 6.42
I/O3L N/C I/O4L I/O5L I/O6L I/O7L N/C GND GND I/O0R I/O1R I/O2R I/O3R N/C I/O4R I/O5R
NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. J52-1 package body is approximately .75 in x .75 in x .17 in. PN64-1 package body is approximately 14mm x 14mm x 1.4mm. PP64-1 package body is approximately 10mm x 10mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
IDT71321/421PF or TF PN64-1 / PP64-1(4) 64-Pin TQFP 64-Pin STQFP Top View(5)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
OER A0R A1R A2R A3R A4R A5R A6R N/C A7R A8R A9R N/C N/C I/O7R I/O6R
, 2691 drw 03
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
IDT71321SA/LA and IDT71421SA/LA High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Capacitance(1)
Symbol CIN COUT
(TA = +25C, f = 1.0MHz) TQFP Only
Parameter Input Capacitance Output Capacitance Conditions(2) VIN = 3dV VOUT = 3dV Max. 9 10 Unit pF pF
2691 tbl 00
Recommended Operating Temperature and Supply Voltage(1,2)
Grade Commercial Industrial Ambient Temperature 0OC to +70OC -40OC to +85OC GND 0V 0V Vcc 5.0V + 10% 5.0V + 10%
2691 tbl 02
NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dv references the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V.
NOTES: 1. This is the parameter TA. 2. Industrial temperature: for specific speeds, packages and powers contact your sales office.
Absolute Maximum Ratings(1)
Symbol VTERM(2) Rating Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature DC Output Current Commercial & Industrial -0.5 to +7.0 Unit V
Recommended DC Operating Conditions
Symbol VCC GND Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 4.5 0 2.2 -0.5(1) Typ. 5.0 0
____
Max. 5.5 0 6.0
(2)
Unit V V V V
2691 tbl 03
TBIAS TSTG IOUT
-55 to +125 -55 to +125 50
o
C C
VIH VIL
____
o
0.8
mA
2691 tbl 01
NOTES: 1. VIL (min.) = -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 10%.
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VCC + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > VCC + 10%.
3 6.42
IDT71321SA/LA and IDT71421SA/LA High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1,4,6) (VCC = 5.0V 10%)
71321X20 71421X20 Com'l Only Symbol ICC Parameter Dynam ic Op erating Current (Bo th Po rts Active ) CEL and CER = VIL, Outputs Ope n f = fMAX(2) Test Condition Version COM'L IND COM'L IND ISB2 Stand by Curre nt (One Po rt - TTL Level Inp uts) CE"A" = VIL and CE"B" = VIH (5) A ctive Po rt Outputs Op en, f=fMAX(2) COM'L IND COM'L IND COM'L IND SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA Typ. 110 110
____ ____
71321X25 71421X25 Com'l Only Typ. 110 110
____ ____
Max. 250 200
____ ____
Max. 220 170
____ ____
Unit mA
ISB1
Stand by Curre nt (Bo th Po rts - TTL Level Inp uts)
CEL and CER = VIH f = fMAX(2)
30 30
____ ____
65 45
____ ____
30 30
____ ____
65 45
____ ____
mA
65 65
____ ____
165 125
____ ____
65 65
____ ____
150 115
____ ____
mA
ISB3
Full S tandb y Current (Bo th Po rts CM OS Leve l Inputs)
CEL and CER > VCC - 0.2V, VIN > VCC - 0.2V o r VIN < 0.2V, f = 0 (3) CE"A" < 0.2V and CE"B" > VCC - 0.2V (5) VIN > VCC - 0.2V o r V IN < 0.2V A ctive Po rt Outputs Op en, f = fMAX(2)
1.0 0.2
____ ____
15 5
____ ____
1.0 0.2
____ ____
15 5
____ ____
mA
ISB4
Full S tandb y Current (One Po rt CM OS Leve l Inputs)
60 60
____ ____
155 115
____ ____
60 60
____ ____
145 105
____ ____
mA
2691 tbl 04a
71321X35 71421X35 Com'l Only Symbol ICC Parameter Dynamic Ope rating Curre nt (Bo th Po rts Active) CEL and CER = VIL, Outputs Op en f = fMAX(2) Test Condition Version COM'L IND COM'L IND ISB2 Stand by Curre nt (One Po rt - TTL Level Inp uts) CE"A" = VIL and CE"B" = VIH (5) Active P ort Outp uts Ope n, f=fMAX(2) COM'L IND COM'L IND COM'L IND SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA Typ. 80 80
____ ____
71321X55 71421X55 Com'l & Ind Typ. 65 65 65 65 20 20 20 20 40 40 40 40 1.0 0.2 1.0 0.2 40 40 40 40 Max. 155 110 190 140 65 35 65 45 110 75 125 90 15 4 30 10 100 70 110 85
2691 tbl 04b
Max. 165 120
____ ____
Unit mA
ISB1
Stand by Curre nt (Bo th Po rts - TTL Level Inp uts)
CEL and CER = VIH f = fMAX(2)
25 25
____ ____
65 45
____ ____
mA
50 50
____ ____
125 90
____ ____
mA
ISB3
Full S tandb y Curre nt (Bo th Po rts CM OS Level Inp uts)
CEL and CER > VCC - 0.2V, VIN > VCC - 0.2V o r VIN < 0.2V, f = 0 (3) CE"A" < 0.2V and CE"B" > VCC - 0.2V (5) VIN > VCC - 0.2V o r V IN < 0.2V Active P ort Outp uts Ope n, f = fMAX(2)
1.0 0.2
____ ____
15 4
____ ____
mA
ISB4
Full S tandb y Curre nt (One Po rt CM OS Level Inp uts)
45 45
____ ____
110 85
____ ____
mA
NOTES: 1. 'X' in part numbers indicates power rating (SA or LA). 2. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using "AC TEST CONDITIONS" of input levels of GND to 3V. 3. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby. 4. Vcc = 5V, TA=+25C for Typ and is not production tested. Vcc DC = 100mA (Typ) 5. Port "A" may be either left or right port. Port "B" is opposite from port "A". 6. Industrial temperature: for other speeds, packages and powers contact your sales office.
4 6.42
IDT71321SA/LA and IDT71421SA/LA High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VCC = 5.0V 10%)
71321SA 71421SA Symbol |ILI| |ILO| VOL VOL VOH Parameter Input Leakage Current
(1) (1)
71321LA 71421LA Min.
___
Test Conditions VCC = 5.5V, VIN = 0V to VCC CE = VIH, VOUT = 0V to VCC, VCC - 5.5V IOL = 4mA IOL = 16mA IOH = -4mA
Min.
___
Max. 10 10 0.4 0.5
___
Max. 5 5 0.4 0.5
___
Unit A A V V V
2691 tbl 05
Output Leakage Current
___
___
Output Low Voltage (I/O0-I/O7) Open Drain Output Low Voltage (BUSY/INT) Output High Voltage
___
___
___
___
2.4
2.4
NOTE: 1. At Vcc < 2.0V leakages are undefined.
Data Retention Characteristics (LA Version Only)
Symbol VDR ICCDR Parameter VCC for Data Retention Data Retention Current VCC = 2.0V, CE > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V tCDR (3) tR(3) Chip Deselect to Data Retention Time Operation Recovery Time COM'L IND Test Condition Min. 2.0
____
Typ. (1)
____
Max. 0 1500 4000
____
Unit V A A ns ns
2691 tbl 06
100 100
____
____
0 tRC(2)
____
____
NOTES: 1. VCC = 2V, TA = +25C, and is not production tested. 2. tRC = Read Cycle Time 3. This parameter is guaranteed but not production tested.
Data Retention Waveform
DATA RETENTION MODE VDR 2.0V
VCC
4.5V tCDR
4.5V tR
CE VIH
VDR VIH
2691 drw 04 ,
5 6.42
IDT71321SA/LA and IDT71421SA/LA High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 5ns 1.5V 1.5V Figures 1,2 and 3
2691 tbl 07
5V 1250 DATA OUT 775 30pF*
*100pF for 55ns versions
5V 1250 DATA OUT 775 5pF*
Figure 1. AC Output Test Load
Figure 2. Output Test Load (for tHZ, tLZ, tWZ, and tOW) * Including scope and jig.
5V 270 BUSY or INT 30pF*
*100pF for 55ns versions
2691 drw 05
Figure 3. BUSY and INT AC Output Test Load
6 6.42
IDT71321SA/LA and IDT71421SA/LA High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Supply Voltage Range(2,4)
71321X20 71421X20 Com'l Only Symbol READ CYCLE tRC tAA tACE tAOE tOH tLZ tHZ tPU tPD Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Output Hold from Address Change Output Low-Z Time
(1,3) (1,3)
71321X25 71421X25 Com'l Only Min. Max. Unit
Parameter
Min.
Max.
20
____ ____ ____
____
25
____ ____ ____
____
ns ns ns ns ns ns ns ns ns
2691 tbl 08a
20 20 11
____ ____
25 25 12
____ ____
3 0
____
3 0
____
Output High-Z Time
10
____
10
____
Chip Enable to Power Up Time (3) Chip Disable to Power Down Time
(3)
0
____
0
____
20
25
71321X35 71421X35 Com'l Only Symbol READ CYCLE tRC tAA tACE tAOE tOH tLZ tHZ tPU tPD Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Output Hold from Address Change Output Low-Z Time
(1,3)
71321X55 71421X55 Com'l & Ind Min. Max. Unit
Parameter
Min.
Max.
35
____ ____ ____
____
55
____ ____ ____
____
ns ns ns ns ns ns ns ns ns
2691 tbl 08b
35 35 20
____ ____
55 55 25
____ ____
3 0
____
3 5
____
Output High-Z Time(1,3) Chip Enable to Power Up Time
(3) (3)
15
____
25
____
0
____
0
____
Chip Disable to Power Down Time
35
50
NOTES: 1. Transition is measured 500mV from Low or High-impedance voltage Output Test Load (Figure 2). 2. 'X' in part numbers indicates power rating (SA or LA). 3. This parameter is guaranteed by device characterization, but is not production tested. 4. Industrial temperature: for other speeds, packages and powers contact your sales office.
7 6.42
IDT71321SA/LA and IDT71421SA/LA High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1, Either Side(1)
tRC ADDRESS tAA tOH DATAOUT BUSYOUT tBDDH (2,3)
2691 drw 06
tOH DATA VALID
PREVIOUS DATA VALID
NOTES: 1. R/W = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition LOW. 2. tBDD delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relationship to valid output data. 3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
Timing Waveform of Read Cycle No. 2, Either Side (3)
tACE CE tAOE OE tLZ(1) DATAOUT tLZ ICC CURRENT ISS tPU 50%
(1) (4)
tHZ (2)
tHZ (2) VALID DATA tPD
(4)
50%
2691 drw 07
NOTES: 1. Timing depends on which signal is asserted last, OE or CE. 2. Timing depends on which signal is de-asserted first, OE or CE. 3. R/W = VIH and OE = VIL, and the address is valid prior to or coincidental with CE transition LOW. 4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
8 6.42
IDT71321SA/LA and IDT71421SA/LA High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temeprature and Supply Voltage Range(4,5)
71321X20 71421X20 Com'l Only Symbol WRITE CYCLE tWC tEW tAW tAS tWP tWR tDW tHZ tDH tWZ tOW Write Cycle Time (2) Chip Enable to End-of-Write Address Valid to End-of-Write Address Set-up Time Write Pulse Width
(3)
71321X25 71421X25 Com'l Only Min. Max. Unit
Parameter
Min.
Max.
20 15 15 0 15 0 10
____
____ ____ ____ ____ ____ ____ ____
25 20 20 0 15 0 12
____
____ ____ ____ ____ ____ ____ ____
ns ns ns ns ns ns ns ns ns ns ns
2691 tbl 09a
Write Recovery Time Data Valid to End-of-Write Output High-Z Time(1) Data Hold Time Write Enable to Output in High-Z
(1)
10
____
10
____
0
____
0
____
10
____
10
____
Output Active from End-of-Write (1)
0
0
71321X35 71421X35 Com'l Only Symbol WRITE CYCLE tWC tEW tAW tAS tWP tWR tDW tHZ tDH tWZ tOW Write Cycle Time (2) Chip Enable to End-of-Write Address Valid to End-of-Write Address Set-up Time Write Pulse Width(3) Write Recovery Time Data Valid to End-of-Write Output High-Z Time Data Hold Time Write Enable to Output in High-Z(1) Output Active from End-of-Write
(1) (1)
71321X55 71421X55 Com'l & Ind Min. Max. Unit
Parameter
Min.
Max.
35 30 30 0 25 0 15
____
____ ____ ____ ____ ____ ____ ____
55 40 40 0 30 0 20
____
____ ____ ____ ____ ____ ____ ____
ns ns ns ns ns ns ns ns ns ns ns
2691 tbl 09b
15
____
25
____
0
____
0
____
15
____
30
____
0
0
NOTES: 1. Transition is measured 500mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by device characterization but is not production tested. 2. For Master/Slave combination, tWC = tBAA + tWP, since R/W = VIL must occur after tBAA . 3. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 4. 'X' in part numbers indicates power rating (SA or LA). 5. Industrial temperature: for other speeds, packages and powers contact your sales office.
9 6.42
IDT71321SA/LA and IDT71421SA/LA High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, (R/W Controlled Timing)(1,5,8)
tWC ADDRESS tHZ(7) OE tAW CE tAS(6) R/W tWZ(7) DATA OUT
(4)
tWP(2)
tWR(3)
tHZ(7)
tOW
(4)
tDW DATA IN
tDH
2691 drw 08
Timing Waveform of Write Cycle No. 2, (CE Controlled Timing)(1,5)
tWC ADDRESS tAW CE tAS(6) R/W tDW DATA IN
2691 drw 09
tEW(2)
tWR
(3)
tDH
NOTES: 1. R/W or CE must be HIGH during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of CE = VIL and R/W= VIL. 3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle. 4. During this period, the l/O pins are in the output state and input signals must not be applied. 5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal (CE or R/W) is asserted last. 7. This parameter is determined to be device characterization, but is not production tested. Transition is measured 500mV from steady state with the Output Test Load (Figure 2). 8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
10 6.42
IDT71321SA/LA and IDT71421SA/LA High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(6,7)
71321X20 71421X20 Com'l Only Symbol BUSY TIMING (For MASTER 71321) tBAA tBDA tBAC tBDC tWH tWDD tDDD tAPS tBDD BUSY Access Time from Address BUSY Disable Time from Address BUSY Access Time from Chip Enable BUSY Disable Time from Chip Enable Write Hold After BUSY
(5) (1)
____
71321X25 71421X25 Com'l Only Min. Max. Unit
Parameter
Min.
Max.
20 20 20 20
____
____
20 20 20 20
____
ns ns ns ns ns ns ns ns ns
____
____
____
____
____
____
12
____ ____
15
____ ____
Write Pulse to Data Delay
50 35
____
50 35
____
Write Data Valid to Read Data Delay (1) Arbitration Priority Set-up Time BUSY Disable to Valid Data
(3) (2)
5
____
5
____
25
35
BUSY INPUT TIMING (For SLAVE 71421) tWB tWH tWDD tDDD Write to BUSY Input(4) Write Hold After BUSY
(5) (1) (1)
0 12
____ ____
____ ____
0 15
____ ____
____ ____
ns ns ns ns
2691 tbl 10a
Write Pulse to Data Delay
40 30
50 35
Write Data Valid to Read Data Delay
71321X35 71421X35 Com'l Only Symbol BUSY TIMING (For MASTER 71321) tBAA tBDA tBAC tBDC tWH tWDD tDDD tAPS tBDD BUSY Access Time from Address BUSY Disable Time from Address BUSY Access Time from Chip Enable BUSY Disable Time from Chip Enable Write Hold After BUSY(5) Write Pulse to Data Delay
(1) (1)
____
71321X55 71421X55 Com'l & Ind Min. Max. Unit
Parameter
Min.
Max.
20 20 20 20
____
____
30 30 30 30
____
ns ns ns ns ns ns ns ns ns
____
____
____
____
____
____
20
____ ____
20
____ ____
60 35
____
80 55
____
Write Data Valid to Read Data Delay Arbitration Priority Set-up Time (2) BUSY Disable to Valid Data
(3)
5
____
5
____
35
50
BUSY INPUT TIMING (For SLAVE 71421) tWB tWH tWDD tDDD Write to BUSY Input(4) Write Hold After BUSY
(5)
0 20
____
____ ____
0 20
____ ____
____ ____
ns ns ns ns
2691 tbl 10b
Write Pulse to Data Delay(1) Write Data Valid to Read Data Delay
(1)
60 35
80 55
____
NOTES: 1. Port-to-port delay through RAM cells from the writing port to the reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY." 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of 0, tWDD - tWP (actual) or tDDD - tDW (actual). 4. To ensure that a write cycle is inhibited on port "B" during contention on port "A". 5. To ensure that a write cycle is completed on port "B" after contention on port "A". 6. 'X' in part numbers indicates power rating (SA or LA). 7. Industrial temperature: for other speeds, packages and powers contact your sales office.
11 6.42
IDT71321SA/LA and IDT71421SA/LA High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read and BUSY(2,3,4)
tWC ADDR"A" MATCH tWP R/W "A" tDW DATAIN "A" tAPS(1) ADDR"B" tBAA BUSY"B" tWDD DATAOUT"B" tDDD
NOTES: 1. To ensure that the earlier of the two ports wins. tAPS is ignored for Slave (71421). 2. CEL = CER = VIL 3. OE = VIL for the reading port. 4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A".
2691 drw 10
tDH
VALID
MATCH tBDA tBDD
VALID
Timing Waveform of Write with BUSY(4)
tWP R/W"A" tWB(3) BUSY"B" tWH (1) R/W"B"
, (2)
NOTES: 1. tWH must be met for both BUSY input (71421, slave) or output (71321, Master). 2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH. 3. tWB is only for the slave version (71421). 4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A".
2691 drw 11
12 6.42
IDT71321SA/LA and IDT71421SA/LA High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Timing Waveform of BUSY Arbitration Controlled by CE Timing(1)
ADDR "A" AND "B" CE"B" tAPS(2) CE"A" tBAC BUSY"A"
2691 drw 12
ADDRESSES MATCH
tBDC
Timing Waveform of BUSY Arbritration Controlled by Address Match Timing (1)
tRC or tWC ADDR"A" tAPS ADDR"B" tBAA BUSY"B"
2691 drw 13 (2)
ADDRESSES MATCH
ADDRESSES DO NOT MATCH
tBDA
NOTES: 1. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (71321 only).
AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1,2)
71321X20 71421X20 Com'l Only Symbol INTERRUPT TIMING tAS tWR tINS tINR Address Set-up Time Write Recovery Time Interrupt Set Time Interrupt Reset Time 0 0
____ ____
71321X25 71421X25 Com'l Only Min. Max. Unit
Parameter
Min.
Max.
0 0
____
____
ns ns ns ns
2691 tbl 11a
____
____
20 20
25 25
____
____
NOTES: 1. 'X' in part numbers indicates power rating (SA or LA). 2. Industrial temperature: for other speeds, packages and powers contact your sales office.
13 6.42
IDT71321SA/LA and IDT71421SA/LA High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Supply Voltage Range(1,2)
71321X35 71421X35 Com'l Only Symbol INTERRUPT TIMING tAS tWR tINS tINR Address Set-up Time Write Recovery Time Interrupt Set Time Interrupt Reset Time 0 0
____ ____ ____ ____
71321X55 71421X55 Com'l & Ind Min. Max. Unit
Parameter
Min.
Max.
0 0
____ ____
____ ____
ns ns ns ns
2691 tbl 11b
25 25
45 45
NOTES: 1. 'X' in part numbers indicates power rating (SA or LA). 2. Industrial temperature: for other speeds, packages and powers contact your sales office.
Timing Waveform of Interrupt Mode(1)
SET INT
tWC ADDR"A" INTERRUPT ADDRESS tAS (3) R/W"A" tINS (3) INT"B"
2691 drw 14 (2)
tWR (4)
CLEAR INT
tRC ADDR"B" tAS(3) OE"B" tINR(3) INT"A"
2691 drw 15
INTERRUPT CLEAR ADDRESS
(2)
NOTES: 1. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 2. See Interrupt Truth Table. 3. Timing depends on which enable signal (CE or R/W) is asserted last. 4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
14 6.42
IDT71321SA/LA and IDT71421SA/LA High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Truth Tables Truth Table I. Non-Contention Read/Write Control(4)
Left or Right Port(1) R/W X X L H H CE H H L L L OE X X X L H D0-7 Z Z DATAIN DATAOUT Z Function Port Disabled and in Power-Down Mode, ISB2 or ISB4 CER = CEL = VIH, Power-Down Mode, ISB1 or ISB3 Data on Port Written Into Memory(2) Data in Memory Output on Port(3) High Impedance Outputs
2691 tbl 12
NOTES: 1. A0L - A10L A0R - A10R. 2. If BUSY = L, data is not written. 3. If BUSY = L, data may not be valid, see tWDD and tDDD timing. 4. 'H' = VIH, 'L' = VIL, 'X' = DON'T CARE, 'Z' = HIGH IMPEDANCE
Truth Table II. Interrupt Flag(1,4)
Left Port R/WL L X X X CEL L X X L OEL X X X L A10L-A0L 7FF X X 7FE INTL X X L
(3) (2)
Right Port R/WR X X L X CER X L L X OER X L X X A10R-A0R X 7FF 7FE X INTR L
(2) (3)
Function Set Right INTR Flag Reset Right INTR Flag Set Left INTL Flag Reset Left INTL Flag
2691 tbl 13
H X X
H
NOTES: 1. Assumes BUSYL = BUSYR = VIH 2. If BUSYL = VIL, then No Change. 3. If BUSYR = VIL, then No Change. 4. 'H' = HIGH, 'L' = LOW, 'X' = DON'T CARE
Truth Table III Address BUSY Arbitration
Inputs CEL X H X L CER X X H L A0L-A10L A0R-A10R NO MATCH MATCH MATCH MATCH Outputs BUSYL(1) H H H (2) BUSYR(1) H H H (2) Function Normal Normal Normal Write Inhibit(3)
2691 tbl 14
NOTES: 1. Pins BUSYL and BUSYR are both outputs for 71321 (Master). Both are inputs for 71421 (Slave). BUSYX outputs on the 71321 are open drain, not push-pull outputs. On slaves the BUSYX input internally inhibits writes. 2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs of this port. 'H' if the inputs to the opposite port became stable after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
15 6.42
IDT71321SA/LA and IDT71421SA/LA High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Functional Description
The IDT71321/IDT71421 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT71321/IDT71421 has an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE = VIH). When a port is enabled, access to the entire memory array is permitted. being expanded in depth, then the BUSY indication for the resulting array does not require the use of an external AND gate.
Width Expansion with Busy Logic Master/Slave Arrays
Interrupts
If the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location 7FE (HEX), where a write is defined as the CER = R/WR = VIL, per Truth Table II. The left port clears the interrupt by accessing address location 7FE when CEL = OEL = VIL, R/W is a "don't care". Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location 7FF (HEX) and to clear the interrupt flag (INTR), the right port must access the memory location 7FF. The message (8 bits) at 7FE or 7FF is user-defined, since it is an addressable SRAM location. If the interrupt function is not used, address locations 7FE and 7FF are not used as mail boxes, but as part of the random access memory. Refer to Truth Table II for the interrupt operation.
When expanding an SRAM array in width while using BUSY logic, one master part is used to decide which side of the SRAM array will receive a BUSY indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the BUSY signal as a write inhibit signal. Thus on the IDT71321/IDT71421 SRAMs the BUSY pin is an output if the part is Master (IDT7132), and the BUSY pin is an input if the part is a Slave (IDT7142) as shown in Figure 3.
DECODER
5V 270
MASTER Dual Port SRAM BUSYL
CE BUSYR
SLAVE Dual Port SRAM BUSYL
CE BUSYR
5V 270
MASTER Dual Port SRAM BUSYL BUSYL
CE BUSYR
SLAVE Dual Port SRAM BUSYL
CE BUSYR BUSYR
2691 drw 16
Busy Logic
Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is "Busy". The BUSY pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a busy indication, the write signal is gated internally to prevent the write from proceeding. The use of BUSY Logic is not required or desirable for all applications. In some cases it may be useful to logically OR the BUSY outputs together and use any BUSY indication as an interrupt source to flag the event of an illegal or illogical operation. In slave mode the BUSY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins HIGH. If desired, unintended write operations can be prevented to a port by tying the BUSY pin for that port LOW. The BUSY outputs on the IDT71321 (Master) are open drain type outputs and require open drain resistors to operate. If these SRAMs are
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT71321 (Master) and (Slave) IDT71421 SRAMs.
If two or more master parts were used when expanding in width, a split decision could result with one master indicating BUSY on one side of the array and another master indicating BUSY on one other side of the array. This would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. The BUSY arbitration, on a Master, is based on the chip enable and address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enough for a BUSY flag to be output from the master before the actual write pulse can be initiated with either the R/W signal or the byte enables. Failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave.
16 6.42
IDT71321SA/LA and IDT71421SA/LA High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Ordering Information
IDT XXXX A Device Type Power 999 Speed A Package A Process/ Temperature Range BLANK Commercial (0C to +70C) I(1) Industrial (-40C to +85C) J PF TF 20 25 35 55 52-pin PLCC (J52-1) 64-pin TQFP (PN64-1) 64-pin STQFP (PP64-1) Commercial Only Commercial Only Commercial Only Commercial & Industrial
Speed in nanoseconds
LA SA 71321 71421
Low Power Standard Power 16K (2K x 8-Bit) MASTER Dual-Port SRAM w/ Interrupt 16K (2K x 8-Bit) SLAVE Dual-Port SRAM w/ Interrupt
2691 drw 17
NOTE: 1. Industrial temperature range is available in selected PLCC packages in standard power. For other speeds, packages and powers contact your sales office.
Datasheet Document History
3/24/99: Initiated datasheet document history Converted to new format Cosmetic typographical corrections Pages 2 and 3 Added additional notes to pin configurations Changed drawing format
6/7/99:
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17 6.42

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